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Chapter 2: Getting Started
2–3
MegaWizard Plug-In Manager Design Flow
6. On the Summary tab, select the files you want to generate. A gray checkmark
indicates a file that is automatically generated. All other files are optional.
For more information about the files generated in your project directory, refer to
the project files list in the HTML report file in your project directory.
7. Click Finish to generate the IP core and supporting files.
You may have to wait several minutes for file generation to complete, especially if
you are generating an IP functional simulation model.
8. If you generate the RapidIO IP core instance in a Quartus II project, you are
prompted to add the Quartus II IP File ( .qip ) to the current Quartus II project. You
can also turn on Automatically add Quartus II IP Files to all projects .
The .qip is generated by the parameter editor, and contains information about the
generated IP core. In most cases, the .qip contains all of the necessary assignments
and information required to process the IP core or system in the Quartus II
compiler. The MegaWizard Plug-In Manager generates a single .qip for each IP
core.
9. After you review the generation report ( < variation name >.html ) in your project
directory, click Exit to close the MegaWizard Plug-In Manager.
You can now integrate your custom IP core variation in your design, simulate, and
compile.
When you integrate your RapidIO IP core variation in your design, note the
connection and I/O assignment requirements described in “Completing the Qsys
System” on page 2–6 .
Simulating the Design
You can simulate your RapidIO IP core variation using the IP functional simulation
model and the Verilog HDL demonstration testbench. The IP functional simulation
model and testbench files are generated in your project directory. The directory also
includes scripts to compile and run the demonstration testbench. The testbench
demonstrates how to instantiate a model in a design and includes some simple
stimulus to control the user interfaces of the RapidIO interface.
For information about the demonstration testbench, refer to Chapter 7, Testbenches .
1
If you specify VHDL for your RapidIO IP core, the IP functional simulation model is
in VHDL, but the testbench is in Verilog HDL. Therefore, you must have a license to
run mixed language simulations to run the testbench with the VHDL model.
Alternatively, you can run simulation in a VHDL-only environment. In a VHDL-only
environment, you must create your own test environment.
To simulate your MegaWizard Plug-In Manager flow generated RapidIO IP core
variation with the IP functional simulation model and the Verilog HDL
demonstration testbench, using the Mentor Graphics ModelSim simulator, perform
the following steps:
1. Start the ModelSim simulator.
2. In ModelSim, change directory to your project directory.
May 2013
Altera Corporation
RapidIO MegaCore Function
User Guide
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